1. Field of the Invention
This invention relates to frequency detection circuits, and more specifically to the design of a circuit capable of detecting the frequency of an external clock source and adjust its internal PLL accordingly.
2. Description of the Related Art
In many electronics systems, especially in synchronous digital circuits, a clock signal, oftentimes also referred to as a trigger signal, is used to coordinate the actions of two or more circuits, and/or to predictably trigger system events. A typical clock signal is a square wave oscillating between a high state and a low state, and generally has a 50% duty cycle. Circuits that use a clock signal for synchronization may become active at either the rising or falling edge of the clock signal, or, as in the case of DDR SDRAMs on both the rising and falling edges of the clock signal.
Most integrated circuits (ICs) that reach a certain level of complexity utilize a clock signal in order to synchronize various parts of the circuit and to effectively manage propagation delays. As the complexity of ICs increases, so does the difficulty of supplying accurate, synchronized clocks to the various circuits and logical blocks within the IC. Examples of complex ICs include microcontrollers and microprocessors, the central components of many modern computers and computer based systems. Microprocessors, for example, typically rely on a clock signal derived from a crystal oscillator. Many times a clock signal may be gated, i.e. combined with a controlling signal that enables or disables the clock signal for a certain part of a circuit. Gated clocks are often used to save power by effectively shutting down portions of a digital circuit when they are not in use.
Most current microprocessors and microcontrollers use internally generated single-phase clock signals that are typically derived from external clock sources (such as crystal oscillators) using Phase Locked Loops (PLLs), oftentimes with a “clock multiplier” configured to multiply the lower frequency external clock source signal to obtain the appropriate clock rate of the microprocessor/microcontroller. This typically allows Central Processing Units (CPUs) to operate at a much higher frequency than the rest of the system, affording performance gains when the CPU does not need to wait on external components/signals like memory or Input/Output (I/O) signals, for example.
For most every IC, the internal PLL clock generation circuit generally requires a fixed clock reference at its startup time. In many cases, due mainly to cost, interoperability, availability, and compliance considerations, it is beneficial for original equipment manufacturers (OEMs) to have the capability of choosing different clock frequencies at system startup. Most IC (or chip) vendors do not have a solution for providing a different clock frequency, thus, IC designers have to retrofit their designs to the single clock source limitation or use different chips. When a solution is offered, it usually requires additional pins and/or control signals, which may not readily be available or affordable in certain IC designs.
FIG. 1 shows an example of a system 100 in which specified pins have been allocated as clock sources, with different pin configurations used for indicating different clock source frequencies. These pins are in addition to the input pins 102 and 104, which may be used for coupling an external clock source or a crystal. Clock mode pin 106 may be used to specify the clock source, which may be a crystal, external oscillator, or some other external periodic signal, and clock select pins 108 and 110 (or, any number of pins from 2 to N) may be used to specify the frequency of the clock source. When allocating clock select pins and clock mode pins for configuring the clock as shown in FIG. 1, in order to support different clock source frequencies the external clock source configuration pins 106, 108, and 110 (and/or any additional clock select pins that may be present) have to be configured correctly. Any error in the pin configurations may result in a PLL failure or malfunction. In addition, the extra pins also increase IC development costs, raising the overall cost of the IC by more than just the cost of the additional pins to the IC package.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.